It is a common practice in the art of integrated circuit design to simulate the operation of a given circuit using simulation software operating in a computer system. Using simulation software allows the circuit designer to verify the operation and margins of a circuit design before incurring the expense of actually building and testing the circuit. Through the use of such simulations, design errors or risks are hopefully identified early in the design process, and resolved prior to fabrication of actual circuits.
One particular application requiring improved modeling and simulation relates to the synchronization of a clock with data in a serial or source-synchronous interconnect, as is illustrated in FIG. 1. Shown generically is a system 10, which includes a transmitter 12 of a clock signal (CLK) and data signals (Data1 through Data_N), and a receiver 14 of such signals. Such devices may comprise in one useful example a memory controller 12 and a memory integrated circuit 14 (such as a Synchronous Dynamic Random Access Memory (SDRAM)) interconnected by interconnects 15 on a printed circuit board.
As one skilled in the art understands, the clock signal is sent by the memory controller 12 along with the data so that the SDRAM 14 can capture the data in synchronization with the clock. Because the data and clock are sent together, it is hoped that noise affecting one interconnect 15 would similarly affect the other interconnects. In other words, by this scheme, it is hoped that noise will cancel at the SDRAM 14, such that a delay (or advance) in receipt of the data at the SDRAM will be negated by a delay (or advance) in receipt of the clock used to capture the data. Such data capture takes place on the SDRAM 14 at sample circuits 16, which might comprise latches for instance.
When such a scheme is used, it is generally preferred that the timing between the data and the clock not be skewed by either the printed circuit board routing or the circuitry internal to the SDRAM 14. To reduce such skew, it is important to consider the effective length that the clock signal must travel internal to the SDRAM 14. To preserve synchronicity, it is desired that the clock signal arrive at each of the sample circuits 16 at the same time. This can be problematic, because certain of the sample circuits 16 (e.g., that serving Data_N in FIG. 1) will be farther from the entry point of the clock signal than are other sample circuits 16 (e.g., that serving Data1).
To reduce such skewing effects, a distribution network 18 can be employed within the SDRAM 14, with the goal of equating the distances that the clock signal must travel to each of the sample circuits 16 (such that L1=L2= . . . =L_N). This means that certain internal clock signals will intentionally need to be lengthened to match the length of the longest of the internal clock signals (L_N as shown in FIG. 1).
The use of a distribution network 18 to reduce data capture skew is generally non-problematic for a relatively slow-speed system. However, at faster data rates, the distribution network 18 can cause misalignment of the cycles between the data and clock signals. For example, assume that the distribution network 18 causes an internal delay equal to 2 nanoseconds (ns). Assume further that the clock signal is a 1 GHz clock (i.e., with a period of 1 ns). The effect of the distribution network 18 would be to delay the receipt of the clock at the sample circuits 16 by two clock cycles. This means that each Nth clock cycle would be used to capture each (N+2)th data signal at the sample circuits 16. This is illustrated in FIG. 2. As can be seen, at the transmitter (memory controller) 12, the clock cycle and data signals are essentially periodically aligned, such that the first clock pulse (CLK1) is transmitted with the first byte (word, etc.) of data (D1). (Actually, in recognition of the necessity of at least some minimal internal clock delay at the receiver 14, the clock cycles may be issued some amount, A, in advance of their corresponding data). However, at the receiver 14, due to the delay in the clock distribution network 18, it can be seen that the first clock pulse (CLK1) captures the third byte of data (D3) at the sample circuits 16 at its rising edge; the second clock pulse (CLK2) captures the fourth byte of data (D4); etc. In short, and as mentioned earlier, this misaligns the data with the clock at the receiver (SDRAM) 14.
While there is nothing wrong with such clock-to-data misalignment at the sample circuits 16 as a general matter, such misalignment is at odds with the assumption that simultaneous transmission of clock and data helps in canceling noise. For example, assume that noise causes simultaneously-transmitted clock and data (CLK_N and D_N) to be delayed by some amount, j(N), where j(N) can be positive (representing a delay) or negative (representing an advance). Such a time shift can generically be referred to as “jitter.” Were such simultaneously-transmitted signals simultaneously received at the sample circuits 16, i.e., a positive correlation, any such jitter j(N) would tend to cancel out, such that the data would be appropriately sampled. However, such cancellation of jitter is not guaranteed when the reality of the distribution network 18, and its associated misalignment, is appreciated. For example, consider the capture of data signals D3, which were delayed (or advanced) (“jittered”) by j(3). In the example illustrated in FIG. 2, such data signals will be captured by CLK1, which has its own jitter of j(1), which, due to the difference in time, might not equal jitter j(3).
Because of the reality of jitter, it becomes important to model or simulate the performance of the sample circuits 16 in light of such jitter, to gauge whether such circuits will satisfactorily sample the incoming data, and with what bit error rate. A simple example of sample circuits 16 are shown in FIG. 3. As shown, an operational amplifier (op amp) 20 compares the received data to a mid-point reference voltage (e.g., ½ the operating voltage Vdd), which is sampled by enabling the op amp 20 on the rising edge of the clock signal, CLK. The output of the op amp 20 (Vout_N) represents a sampled version of the input data (Data_N). By simulating the operation of the sample circuits 16 in light of any jitter that might be present on the clock and data inputs, a designer can tell how tight sensing margins are for the sample circuit 16, and/or the expected bit error rate of the sample circuit 16.
A particularly difficult problem in the context of simulation of sample circuits involves the real possibility of periodic jitter, i.e., jitter that causes the timing of the signals to vary or oscillate in a periodic manner from cycle to cycle. Forms of periodic jitter are common in realistic systems, where regular data and/or clock combinations excite resonant modes in the transmitters or receivers (or their integrated circuit (IC) packages) that translate into jitter on the edges of the traveling signals. Most often the periodicity is first observed in the clock signal, but is then transferred to the data signals as the data bits are re-timed and launched by the jittery clock edges. Efficient modeling of such periodic jitter is therefore useful to a circuit designer, and as will be seen below, is particularly useful in modeling the bit error rates of the sample circuits 16 and their associated links.
Periodic jitter is shown in FIG. 4 with reference to a clock signal, in which an ideal (non-jittered) clock signal is shown in solid lines, with a periodically-jittered clock shown in dotted lines for comparison. Because the sample circuits 16 illustrated above only sample data on the clock's rising edges, periodic jitter in FIG. 4 is only illustrated with respect to clock's rising edges for simplicity. However, the falling edges could also be used to sample the data, as is done in double-data rate (DDR) systems, and such falling edges could similarly be affected by periodic jitter. The graph at the bottom of FIG. 4 shows the magnitude of the jitter, j(i), from its otherwise ideal value as a function of the ith rising edge (or each ith cycle) of the clock. The jitter, j(i), is a measure of time, and may be on the order of picoseconds for example. As the graph illustrates, the jitter is indeed periodic, and in this case, more specifically, is sinusoidal.
Even if the DC skew or gross timing of the arrival of the data and the clock at the sample circuits 16 is optimized for perfect alignment, the phase difference in the periodic jitter between the data and the clock may not enjoy a good correlation. For example, if the phase difference between the jitter on the data and on the clock is 180 degrees (i.e., negatively correlated), the periodicity of the jitter may cause the data to arrive maximally early at the sample circuits, while the clock arrives maximally late, or vice versa. Such negative correlation can substantially reduce sensing margins at high data and clock rates.
Unfortunately, simulating the effects of periodic jitter is not easy to accomplish. Particularly, because of the clock distribution network 18's effect on the clock signal prior to receipt at the sample circuits 16, it would generally be necessary to construct the distribution network 18 prior to running the simulation. This is undesirable, both because it requires additional work, and because simulation may actually be useful in optimizing the distribution network 18 to achieve a suitable bit error rate at the sample circuits 16. In short, an improved technique, one that is not so laborious, is preferred, and is disclosed herein.